(a) Field of the Invention
The present invention relates to a variable delay circuit and, more particularly, to a variable delay circuit for providing a variable delay time capable of being controlled by a set of control signals.
(b) Description of the Related Art
A variety of variable delay circuits have been proposed each providing a variable delay time capable of being controlled by a set of control signals supplied from outside the circuit. Since the variable delay circuit can be designed to implement a voltage controlled oscillator by connecting the output of the variable delay circuit with the input thereof for a negative feedback loop, it is sometimes described as a programmable voltage controlled oscillator.
U.S. Pat. No. 4,978,927 to Hausman et al. discloses a programmable voltage controlled oscillator shown in FIG. 1. The voltage controlled oscillator has three basic gate circuits 202, 204 and 206, a first gate circuit 232 and a second gate circuit 226, all of which are connected to form a ring oscillator, with one of two signal paths in each of the basic gate circuits 202, 204 and 206 being selected by selecting a set of control signals "A", "B" and "C" to selectively short-cutting a signal path portion of the ring oscillator. By this configuration, the voltage controlled oscillator achieves a variable oscillator frequency.
Patent Publication JP-A-5(1993)-268002 proposes another voltage controlled oscillator shown in FIG. 2, wherein a NAND gate 305 including an associated transistor N52 and a plurality of inverters 301 to 304 each including an associated transistor N12, N22, n32 or N42 are cascaded, with the output of the last stage inverter 304 being fed-back to the first input of the NAND gate 305. The current of each of the NAND gate 305 and inverters 301 to 304 is controlled by the associated transistors receiving an analog control signal "IN" for controlling the ON-resistance of the associated transistors, thereby obtaining a variable delay time in the voltage controlled oscillator. The NAND gate 305 also receives a control signal CR through the second input thereof for starting or stopping the oscillation. In this configuration, a wide range of oscillator frequency can be obtained.
In the conventional voltage controlled oscillators as mentioned above, there is a problem in that the gains of the voltage controlled oscillators of the same design differ from each other due to the variation caused by a fabrication process or the gain of a voltage controlled oscillator changes with the change of the operational temperature. This is common to a digital circuit and an analog circuit. The term "gain" as used herein means the ratio of the amount of the change in the resultant delay time to the amount of the change in the control signal (set of control signals), which may be expressed in terms of either analog or digital magnitude, supplied to the voltage controlled oscillator which is operating to provide a desired delay. For example, the delay of a typical basic gate formed by transistors generally ranges between about 0.5 times and 2.0 times normal delay, which involves the gain of the voltage controlled oscillator ranging between 0.5 and 2.0.
In addition, in the voltage controlled oscillator disclosed in U.S. Pat. No. 4,978,927, the delay can be controlled stepwise specified by a unit time corresponding to the delay of each basic gate circuit. Accordingly, a finer adjustment cannot be obtained. This is peculiar to the case of the digital circuit. For example, the delay of a basic gate is about 100 pico-second (ps) in the case of 0.2 .mu.m CMOS-LSI ata source voltage of 2.5 volts, which limits the unit delay to 100 ps.
In the case of the voltage controlled oscillator described in JP-A-5-268002, since the control range is limited by a source voltage, a higher gain causes the oscillator to be more susceptible to noise. This is peculiar to the case of an analog circuit. Specifically, the control range of an analog control signal generally depends on the source voltage. Accordingly, if a wide range of the delay is desired for the voltage controlled circuit, it is generally achieved by a large gain of the voltage controlled oscillator, which causes that only small noise in the control signal generates large noise in the output delay.